1. Field of the Invention
The present invention relates to a semiconductor device having a plurality of parallel conductive layers, such as word lines, and a plurality of backing conductive layers for substantially reducing the resistance of the conductive layers.
2. Description of the Related Art
In a prior art semiconductor device such as a prior art semiconductor memory device, where a plurality of parallel conductive layers, such as word lines, are provided, as the integration has advanced so that the conductive layers are fine structured, the resistance of the conductive layers becomes large. In order to reduce the resistance of the conductive layers, backing conductive layers are provided in parallel with the conductive layers, and are electrically connected to the conductive layers via contact holes at an insulating layer therebetween.
In the above-mentioned prior art semiconductor device, however, since the backing conductive layers are wider at the contact holes, it is impossible to reduce the pitch of the backing conductive layers, and as a result, it is impossible to reduce the pitch of the conductive layers. This will be explained later in detail.